A soft error upset (SEU), also known as a single event upset, refers generally to a change of state or a transient induced in one or more signal values in a semiconductor device (e.g., when struck by an ionizing particle, such as a neutron or an alpha particle). For example, a programmable logic device (PLD), such as a field programmable gate array (FPGA) or a complex PLD (CPLD), are configured by data stored in configuration memory cells (e.g., SRAM cells), which are susceptible to SEUs that change the originally programmed data state (e.g., programmed a “1” but SEU changes value to “0”). One or more SEUs within the PLD may be particularly noticeable because the data stored in the configuration memory cells determines the PLD's functionality.
Consequently for example, a conventional PLD typically includes soft error detection (SED) logic (e.g., soft error intellectual property (IP)) that will read the configuration memory cells, such as in the background of a user mode of operation, and calculate a cyclic redundancy code (CRC) value to compare with a pre-calculated CRC value (e.g., CRC checksum). If the CRC values match, then there is no error in the values stored in the configuration memory cells. However, if the CRC values do not match, an error flag may be provided, which may for example trigger a reconfiguration of the PLD.
To test the SED logic's ability to detect a soft error (e.g., SED logic functionality), a typical procedure is to simulate a soft error in the PLD as it is may be difficult to produce a real soft error in the hardware. For example, associated logic may be provided to the SED logic to simulate a soft error from one or more configuration memory cells, such as by changing a data value after it has been read from the configuration memory cell but before the CRC calculation is performed. However, the simulated soft error is not a true soft error condition and thus, may not accurately simulate and properly emulate a real (i.e., true) soft error, such as for example with respect to timing or other considerations.
As a result, there is a need for improved techniques for testing SED logic of programmable logic devices.